The present invention relates generally to decoupling capacitors. More particularly, the present invention relates to the manufacturing of a structure comprising a decoupling capacitor having a metal based carrier.
As substrate packages for integrated circuits on semiconductor chips become denser and faster, there has been a significant increase in the requirements that the newer substrate packages need to meet. For example the substrate packages designed for microwave applications involve high power density chips and interconnections requiring high currents. This imposes severe restrictions in terms of thermal management and also current carrying capability, on these substrate packages. The substrate packages aimed at applications especially in communications need to be thin and highly brazable. Also, certain electrical design requirements dictate that the backside of the substrate packages be metallized for providing a ground cage and slot line type transmission lines be made by embedding large area metal features in the dielectric layer. The substrate packages for digital applications require denser and denser wiring, requiring finer features (lines and vias) to be incorporated at lower costs. There is also a strong drive to reduce the defect density in both the chip carriers and in the passive components in the substrate packages.
The conventional method to build such substrate packages (SCM""s and MCM""s) utilizes multi-layer-ceramic (MLC) processing. This involves making green sheets from the dielectric powder of choice, screening those green sheets with paste(s) of selected metallization to produce patterns and through sheet connections, or vias, stacking these screened green sheets, laminating the green sheets, and then sintering the green sheets to form a three-dimensionally connected substrate package. Sintering large size substrate packages with the very high metal loading, typically required for the communications packages, creates considerable difficulties in controlling the shrinkage, distortion, and flatness of substrate packages at the end of the process. Special processing steps have to be added to assure the flatness of the substrate packages. Also, the backside metallization required to build conventional substrate packages is done by a combination of physical deposition methods and electroplating. The high tolerance required for fabricating substrate packages with very fine features cannot be increased beyond a certain limit due to the distortion of green sheets during various processing steps. Overall processing costs of the substrate packages produced using MLC techniques are relatively higher because of the longer cycle times. Therefore there is a need to develop cost effective ways to produce such substrate packages.
In some substrate packages, decoupling capacitors are required as part of the substrate package to enhance the performance of the chip. New decoupling capacitor designs which enable low inductance paths to the chip yet deliver high capacitance without consuming expensive real estate on the substrate, are the preferred solution, particularly as chip frequencies increase. Thus, what is needed is a decoupling capacitor that has a high dielectric constant combined with a low thickness of the film. Preferably, the decoupling capacitor is simple to manufacture, is flexible to accommodate a wide variety of chip designs, and does not use up valuable real estate on the substrate package, compared with prior art techniques.
An aspect of the present invention is a process for fabricating a structure using a metal carrier and forming a double capacitor structure. The process comprises forming a first via hole through the metal carrier, forming a dielectric layer around the metal carrier and inside the first via hole, forming a second via hole through the dielectric layer and the metal carrier, and filling at least one of the via holes with conductive material. In one preferred embodiment, the process further comprises forming a third via hole through the metal carrier before the forming of a dielectric layer, wherein the dielectric layer is formed around the metal carrier, inside the first via hole, and inside the third via hole. The first via hole, the second via hole, and the third via hole are all filled with a conductive material. In one preferred embodiment, the dielectric layer comprises a top surface opposed to a bottom surface, and electrodes are formed on at least one of the top surface and the bottom surface of the dielectric layer.
Another aspect of the present invention is a process for fabricating a substrate package using a metal carrier and forming a single capacitor structure. The process comprises forming a first via hole through the metal carrier, forming an dielectric layer around the metal carrier and the first via hole, wherein the dielectric layer comprises a top dielectric layer opposed to a bottom dielectric layer, removing the top dielectric layer, and filling the first via hole with conductive material. In one preferred embodiment, the process further comprises forming a second via hole and a third via hole through the metal carrier. The second via hole and the third via hole are filled with conductive material. In one preferred embodiment, the dielectric layer comprises bottom surfaces, and the electrodes are formed on at least one of the metal carrier and the bottom surfaces.
These and other aspects of the invention will become apparent upon a review of the following detailed description of the presently preferred embodiments of the invention, when viewed in conjunction with the appended drawings.